# Low Cost 4D Digital Imaging Radar

## Product Technical Brief

### Overview

The S81 is a low cost, fully software defined 4D Imaging Radar-on-Chip (RoC) with Digital Code Modulation (DCM), certified for use in key automotive safety applications such as automatic emergency braking, lane change assist, adaptive cruise control, and blind-spot detection, as well as automated driving functions for autonomous vehicles.

The RoC is provided with system tools and production-ready software APIs to enable quick time-to-market for customers.

The DCM-based imaging radar provides a rich point cloud output for use in long, mid, and short-range applications with high contrast resolution (HCR) to deliver maximum discrimination and high-confidence detection of independent small targets. Furthermore, the DCM technology enables improved interference mitigation and is inherently hack resistant to spoofing.

### Key Features

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- **76-81 GHz Frequency Range**  
- **4D Digital Imaging Radar:** Simultaneous Measurement of Range, Velocity, Azimuth, and Elevation Angle  
- **Up to 96 Virtual Receive Channels (VRx) – True MIMO**  
- **8 Receive Antenna Channels (Rx)**  
- **Up to 12 Transmit Antenna Channels (Tx)**  
- **High Contrast Resolution**  
- **Hack Resistant to Radar Spoofing**  
- **Software Defined Frame and Scan Configuration**  
- **Advanced Interference Mitigation**  
- **Supports ASIL-B Functional Safety (ISO 26262)**  
- **AEC-Q104 Qualified**  
- **Supports user Algorithms On-Chip with High Performance CPU and DSP Cores**  
- **ASPICE Qualified SDK with Ready-to-Integrate APIs**  
- **Imaging Radar for Automated Driver Assistance Systems (ADAS)**. Examples:

### Target Applications

- **Pedestrian Automatic Emergency Braking (P-AEB)**  
- **Low Power Consumption**  
- **Lane Change Assist (LCA)**  
- **Supports Multichip Cascading**  
- **Blind Spot Detection (BSD) and Cross-Traffic Detection (CTD)**  
- **Autonomous Vehicles (AVs)**

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### Key Specifications

| S81 Radar-on-Chip (RoC)                                   | Value                             |
|----------------------------------------------------------|-----------------------------------|
| Center Frequency                                         | 76-81GHz                          |
| Channels                                                 | Up to 12Tx&8Rx                    |
| Tx Output Power                                          | 12dBm                             |
| Maximum Modulation Bandwidth                             | 1GHz                              |
| Noise Figure (NF)                                       | 10dB                              |
| On-Chip Memory                                          | 16MB                              |
| External Memory                                         | Up to 2GB LPDDR4[Up to 32-bit@4266MHz] |
| Compute Processing Cores                                 | 2 ARM Cortex-R5F CPUs@667MHz     |
| Digital Signal Processing (DSP) Cores                   | 2 Tensilica-P5 DSPs@533MHz       |
| Chip Control Processor and Functional Safety Manager     | ARM Cortex M0+ CPU@400MHz with Lockstep Configuration |
| Security (Secure Boot, Interference, Updates)           | Hardware Security Module (HSM)    |
| I/O Interfaces                                          | 3x100/1000 Ethernet, 2x CAN-FD, 2x I2C, QSPI, GPIO |
| Power Consumption                                       | Typical 9W @ 50% Duty Cycle      |
| Package                                                 | 12.8mm x 8.21mm eWLB (wafer level chip scale package) |
| Temperature Range (Tj)                                  | -40℃ to +125℃                    |

1 Typical

### Typical Application Block Diagram

S81 RoC